# Chiseling out The Chip!

This post may be a bit redundant with the info I added in the other place, but I am excited, so I felt the need to rewrite some of it here.

Le Chip! This work took a while. To celebrate, I thought it deserves a few words in the blogs. During the past year or so, I was/have-been/will-continue-to-be working on an image sensor ADC testchip. It was finally taped out yesterday! What’s left now is some additional gastronomical work on the tapeout cake and the drainage of a rusty bottle of champagne.

The chip in all its ugly majesty with all these redundant power pads and LVDS pairs.

The core of the testchip is a fast 12-bit column-parallel ramp ADC at 5u pitch, utilizing some special counting schemes to achieve the desired 1us ramp time at slow clock rates. Alongside, to be able to fully verify the pipelined CDS functionality and crosstalk, I’ve built a pixel array in line-scan configuration, some fast LVDS drivers, clock receivers, references, state machines, a few 8-bit iDACs, bond pads, ESD, and some other array-related stuff, all from scratch! The chip has a horizontal resolution of 1024 and 128 lines with RGBW color filters and microlenses.

On the top-left corner there are some experimental silicon photomultipliers and SPAD diodes. These I plan to measure for fun and I promise to post the results in any of the two blogs.

Unfortunately, this chip wouldn’t yield tons of publicaiton work, apart from the core ADC architecture and comparator. To test the ADC one needs a whole bunch of other fast readout blocks, which in the end are not something novel, but yet, one needs them and designing these takes time. Finishing up this test system was a lot of work and I realize that it might be a bit risky and ambitious to be doing this as part of a doctorate. What if it fails to work because a state machine had an inverted signal somewhere? Or the home-made ESD and pads suffer from latch-up? Or the LVDS driver CMFB is unstable and I cannot readout data out? Or there is a current spike erasing the content of the SRAM? Or, or, or ?

We university people don’t have the corporate power to tapeout metal fixes twice a month until we’re there. I probably have another two or three chip runs for my whole doctorate. It may therefore be better (and more fun) to stick with small but esoteric modules, which one can verify separately and have time to analyze in detail. But hey, I’ll quote a colleague here: “It is what it is, let’s think how we can improve things.”

Finally, I have added this little fella who I hope will be my lucky charm.

Mr Le Duck!

With his 15um of height, could he compete in the annual “smallest duck on the planet” contest? Cheers!

# Random “stuff” about silicon photomultipliers and avalanche diodes

This writing may be considered as a very random continuation of an older post briefly mentioning the usage of photomultiplying tubes for gamma spectroscopy, but the truth is that it is so random that could be impossible to follow. I have some spare 300x600um silicon space and have been recently thinking how to fully utilize the area on the chip I am about to tapeout. Apart from having a free corner of silicon, unfortunately, time is not infinite nor free either (what?) and I have just about a week to think, analyze and engineer whatever it would be. This is why I am also posting this, hoping that in the process of writing/re-reading, I would suddenly get that brilliant idea which would vanish all first world problems and get me through academia obscura.

Back to the point. Some 5 years ago, the image sensors field suddenly realized that instead of trying to integrate the current/electrons from photo-electron pairs in the form of a stored charge on a capacitor, one could initiate an ionization process triggered by a single photon in a very high/concentrated electric field PN junction, a process often referred to as impact ionization. The last is essentially the same as the photomultiplying effect in vacuum tubes, now with the difference that the medium where the process occurs is silicon, plus some additional second order effects. The old, photon-hit-electron-integrate-readout, is a technology which has been here for decades, and still impresses us with its mature-immatureness. How is impact ionization a better solution than the conventional? The answer is – it’s not (for now), and it depends.

Here is my simple explanation of why impact ionization detectors, also called Single Photon Avalanche Diodes (SPADs) should theoretically perform better under low light conditions than the conventional technologies. In electronics, we often use the Friis formula, which states that to minimize the noise figure in a signal chain, we should apply gain in the system as early as possible, and/or perform the less noisy operations first:

$F_{total} = F_1 + \frac{F_2-1}{G_1} + \frac{F_3-1}{G_1 G_2} + \frac{F_4-1}{G_1 G_2 G_3} + ... + \frac{F_n - 1}{G_1 G_2 ... G_{n-1}}$

It is very intuitive, and it could be applied to the signal chain of an image sensor too, even though that the signal chain begins with a noisy source of photons (photon shot noise), distorted by microlenses, attenuated by color filters, converted to electrons with noise, electrons to voltage (?) and voltage to a digital number. Most ultra low-noise CMOS image sensors use the so called High Conversion Gain (HCG) pixels. In simple language, this means that their integration capacitor (FD – floating diffusion) is minimized as much as possible compared to the photodiode junction capacitance. This results in a larger voltage swing on the integration capacitor (FD) per hit photon, which is basically equivalent to maximizing the gain at the very beginning of the photon-electron conversion process. Remember the Friis formula?

Why does a SPAD look promising for ultra-low-light imaging? Avalanche photodiodes, basing on impact ionization have an enormous gain, thus, a single photon can push the trigger causing the diode to hit the rail. Makes life easier for the rest of the measurements too, instead of a complex ADC, we can just use a counter. Sounds brilliant, however, there are some difficulties which prevent us from reaching perfect photon counting. Here’s a small list which I am thinking about right now:

1. The gain in a SPAD may be considered infinite, according Friis the output should be noise-free. However, SPADs, for now, are triggered not only by photons, but also by random thermal excitation and defect traps, sudden releases and gamma ray impact with electrons. The main quality parameter of a SPAD is its so called Dark Count Rate (DCR), or false triggers per time unit under dark conditions. This is a very primitive measurement, however, until now there is no good method for quantifying what part of the DCR is caused by the respective aforementioned side effects.
2. After initiation of avalanche breakdown, in order to arm the diode for another measurement round, we need to cut its power supply and then gradually apply high reverse bias voltage again. The time used for the operation is called reset time. This reset (dead) time is the major obstacle for achieving full single photon detection for high light intensities.
3. SPADs work under high reverse bias voltage conditions which makes them a hard to integrate with readout electronics on 1v2/3v3 CMOS processes, while still keeping a low reset time contribution from the readout.
4. SPAD structures can be easily implemented in standard CMOS and this has been done by a number of research teams during the past 5 years.
5. Most of the researchers are working on SPADs for Time of Flight (ToF) imaging, or ultra-low-light sensing.
6. Most of the research is done on multi-channel readout, which is actually the way to go, but is very challenging in a 2D process (no 3D stacking).
7. Can we use multiple arrays, but have a single readout?
8. Do we now have access to hundreds of PM tubes on a single chip? What could we use these for?

Access to hundreds of “PM tubes” on a single chip? – we call that a silicon photomultiplier (SiPM). Such have existed for a long time and are offered as discrete components, however, the information from each PM is hard to measure, all PMs share the same bus and we get a very difficult for measurement output current. Difficult, in a sense that is noisy and hard to distinguish. Conventional readout of SiPMs integrate and low-pass filter the output current before performing measurement/digitization. To grasp what I am referring to, here’s a simple electrical equivalent diagram of a SiPM:

Silicon Photomultiplier equivalent diagram

You essentially see a number of SPAD diodes with passive quench (the resistor in series) which acts as an automatic reset. When the diode fires the resulting high in-rush reverse bias current causes voltage drop on R (and the SPAD’s cathode respectively) which acts as a feedback mechanism and prevents the avalanche breakdown from continuing, thus resetting the diode by gradually increasing the cathode voltage. Typically SiPMs on the market have passive quench (resistor in series) with the SPADs, the latter are connected in parallel an could reach a relatively large number in the order of 100-1000s. The order depends on their dark and firing current and well as desired photosensitivity. To help you get an idea of how a SiPM should look physically, here’s an example of a small 8×8 SPAD array in SiPM configuration I just sketched in Virtuoso:

An 8×8 diode Silicon photomultiplier array layout diagram

The circular shape of the junctions comes from the fact that we want to have a strong electric field around the junction which should make the diode more susceptible to avalanche breakdown. Ideally it should be entirely circular, in the case above I’ve used hexagonal shape as this CMOS process does not alow other than 45/90 degree angles. Using hexagonal diodes generates stress electric field points which increases the dark count rate. One possible structure for SPAD formation in standard triple-well CMOS is a junction between a NW/DNW and a local P-Well created over the Deep N-Well. The latter local P-Well has the shape of a doughnut and acts as an electric field concentrator. Here’s a cross section sketch:

The thickness of the P-Well doughnut determines the strength of the electric field imposed from the N-Well surrounding doughnut to the P+ active N-Well junction. The multiplication area is formed under the island in the center of the diode. The surrounding material around the active area can be covered with top metal layers to block light and prevent PE pair stimulation outside of the intended junction. Typical SiPMs include a poly quenching resistor which surrounds the SPAD and typically have rectangular shape. In standard CMOS however, apart from the passive quench methodology, we can do all sorts of active quench circuits. What if we combine those in a SiPM? Would such a combination make the integrated current measurements easier?

The last questions remain open, likewise this random post too. Let’s see what I may come up with in the next few remaining days and hope that there would be a follow-up post containing some experimental results.

Oh, by the way, if you want to read an excellent introductory material on SiPMs, check out this link.

# Circuit diagram symbols from circuitikz

When it comes to drawing circuit diagrams for publication work (e.g. books, articles, posters) there has always been a dilemma around which drawing methodology to choose. Everyone wants to have superior quality schematic diagrams, designed in zero or negative time. The pool of drawing tools for circuit diagrams in the galaxy of internet is so huge, and yet, I have not seen any well integrated and universal tool for this simple task of drawing lines and connecting dots. As with many open-source tools, what seems to be missing is a “good integration”, this “good integration” however, appears to be a hard NP-complete problem.

With this post I am not getting any further with the solution of the problem, but I wanted to share a crude solution for creating tikz-like quality circuit diagrams, without having to spend days in tikz coding like a monkey to create a simple RC schematic. If you are not familiar with tikz and the circuitikz package, click on the links to read more.

Going straight to the point – here is a pdf file containing a “database card” of all available till this date circuitikz symbols. Of course, you can find the symbols in the package documentation, however, these are spread among the 60 page manual which is rather difficult for indexing and import in Inkscape.

Now when I have a compressed document with all symbols, I can easily import the ones I need in Inkscape and continue drawing the usual way. Here is the tikz input file used for generation.

And in case you need a high resolution raster version of the database you can find one below.

circuitikz v.0.3 database card

# Energy in a lightning strike

Summertime in Bulgaria is often befallen by thunderstorms involving a large number of lightning strike hits towards the ground, causing damages every year . This made me think about the energy stored in an average lightning bolt. What if we can capture and store it using a “lightning bolt farm”? Would it solve the world’s energy problems? Even Doc Brown used lightning bolts to power the De Lorian so that Marty can get back to 1985. Sounds as a promising energy source, but is it? Here are some of my very primitive thoughts:

According to some online sources an average lightning strike has an energy of 0.5 to 5 Giga Joules [1]. This energy of course, is released for time in the order of microseconds and capturing it is difficult and not the scope of this post. Let’s say that we can capture and store a 2.5 GJ lightning bolt. How much is this and would it be enough? According to Wikipedia the average energy density of coal is roughly 24 Mega Joules per kilogram. This yields roughly 100 kg of coal per lightning bolt. A few dozens of lightning bolts per storm brings us about 1 Ton of coal, not bad…

Assuming a 100 % capture efficiency ten lightning bolts can potentially bring us:

$E_{kWh} = \frac{2.5 GJ}{3600000} = 694 kW/h$

Comparing it to Bulgaria’s one and only nuclear power plant the ten lightning bolts’ energy forms about 0.03 % of its total power capacity as of today. Pretty low, hmm, so we need to capture more of them, just about 30 000 lightning strikes to achieve the same energy capacity… every hour! And this is to cover only one nuclear power plant, which is by far not enough even only for Bulgaria’s needs.

How much crude oil barrels are there in a lightning bolt?

One barrel of crude oil has an equivalent energy of 6 GJ/barrel. So, 1/2 barrel/lightning. The daily petrol consumption in the United States according to their U.S. Energy Information Administration for 2014 is 20 Million barrels per day. Thus, we need about 40 Million lightning strikes per day to satisfy America’s petrol needs. I wonder if EIA’s information can be trustworthy, but 40 M lightning strikes have an equivalent of about 1000 Bulgarian nuclear power plants used at full capacity for one hour every day in the US? On the other hand, it might not be that surprising. America has a population of about 300 million, even if half of its residents drive their cars about 50 miles every day, this is some 750 Million miles/day or in human units 1207 Million km/day. An average car burns 6l/100km and from there we get the number of 2 Million litres of, say gasoline. Assuming that with cracking processes [5] we can distil 20% gasoline out of a unit crude oil, we roughly reach the reported number of 20 Million barrels/day.

With the last fact it becomes apparent that humanity is not going to be powered by lightnings, at least not in the near future, however there is some ongoing research on the topic [2],[3],[4].

Last, a fun assumption. How many electrons are there in an average lightning strike?

2.5 Giga Joules converted to electron volts is:

$\frac{2,5 GJ}{q} = \frac{2,5 GJ}{1,602.10^{-19}} = 1,56.10^{28} eV$

If we assume that the 2.5 GJ work needs to move the electrons on a 1 Mega Volt potential (between the cloud and the ground), this yields:

$\frac{1,56.10^{28} eV}{1 MV} = 1,56.10^{22} \text{ electrons}$

Not a very meaningful comparison, but the average full-well capacity of a pixel in a standard CMOS image sensor is 20 000 electrons. 🙂

References:

[1] Yasuhiro Shiraishi; Takahiro Otsuka (September 18, 2006). “Direct measurement of lightning current through a wind turbine generator structure”. Electrical Engineering in Japan 157: 42. doi:10.1002/eej.20250. Retrieved 24 July 2014.

[2] Bhattacharjee, Pijush Kanti (2010). “Solar-Rains-Wind-Lightning Energy Source Power Generation System” (PDF). International Journal of Computer and Electrical Engineering 2: 353–356. doi:10.7763/ijcee.2010.v2.160. Retrieved March 20, 2014.

[3] Knowledge, Dr. (October 29, 2007). “Why can’t we capture lightning and convert it into usable electricity?”. The Boston Globe. Retrieved August 29, 2009.

[4] Helman, D.S. (2011). “Catching lightning for alternative energy”. Renewable Energy 36: 1311–1314. doi:10.1016/j.renene.2010.10.027. Retrieved March 5, 2013.

[5] James. G. Speight (2006). The Chemistry and Technology of Petroleum (4th ed.). CRC Press. ISBN 0-8493-9067-2.

# Applied chaos theory

Today I am having fun with a very nerdy circuit – Chua’s circuit. An electronic circuit that exhibits chaotic behaviour. I had a hard time getting this circuit to oscillate, but finally, after some prayers, throwing beans and doing black magic here it is:

Chua’s circuit

Heheh, looks terrible, but works. Here are some cool pictures of the Lorenz attractor. I was not able to spread the two twirls further, as my LC tank (in fact gyrator-capacitor tank) would stop oscillating.

Lorenz attractor curves tiral 1

Lorenz attractor curves tiral 2

Lorenz attractor curves tiral 3

Lorenz attractor curves tiral 4

And in case you also want to see how it sounds like and what my setup was here’s a short video clip:

# How long are your wires?

Lately I have been busy working on my analog to digital converters, I have gotten up to the phase of laying out the transistors and interconnect. A question struck me – how long are my wires? I mean, the total sum of lengths of all my wires? Usually the average bus length does not exceed a few hundred micrometers before the signals are being re-buffered, but we have hundreds, if not thousands of them sometimes. To illustrate what I mean, let’s have a sneak on my chip’s interconnect:

Here are a few of the metal layers shown separately. Sorry, can’t afford to show you the rest of the system and more than the metal layers as it’s still a secret, shhh… : )

A close view of vertical interconnect

Vertical interconnect

Horizontal interconnect

A close view

Horizontal interconnect two

Considering the fact that some SoCs can have up to 16 metal layers, we can continue our list forever. Notice the ruler showing the scale of the first figure, the unit is in micrometers. I was wondering what is the best way to calculate all sums, however Domenico Pacifici has done this analysis in his PhD thesis before me and I dare to reprint one of his figures.

Total interconnect length in km/cm2 vs year of process development

Wowsh, I had guesses that it may be in the order of hundreds of meters, but 10km? Also notice the log scale, nicely matching with Moore’s law. Remember also that in 2008 the cutting-edge process nodes were at about 90 to 65nm. Some large SoCs may reach areas of about 5 $cm^{2}$, this means that the computer chips we have in an average town contain enough wire to probably reach the Moon? Impressive! Now keep calm and continue pushing polygons!