# ATLAS silicon strip detectors and charge sensing

Some time ago, scientists at the Large Hadron Collider (LHC) at CERN reported the potential discovery of a new fundamental particle, which does not fit anywhere in the standard model of physics. According to “the news”, the latest data from ATLAS and CMS (LHC’s two largest detectors) shows two unexpected data “bumps” from the usual gamma-ray flashes, which are correlated and acquired from two separate detectors. According to physicists, this may point to the existence of a particle that dwarfs by light-years even the recent discovery of gravitational waves.

It is not yet sure if this measurement data would get confirmed or rejected, but the latest news point that the significance of the results is fairly low, owning a sigma of 1.6 approximately. That fact inspired me to write a bit about the basics of the basics in silicon strip detector charge sensing, which is a stone age technology in commercial light sensing CMOS image sensors nowadays.

So what are strip detectors and how are they used? These are basically PN-junctions with an extremely wide aspect-ratio and, as their name suggests, look like strips. Here’s a sketch:

A bird’s eye view of silicon strip detectors

These strips usually share an N-type substrate while each is P+ doped, covered by aluminium with some extra insulation layers in between. The LHC scientists are interested in observing interference patterns in X and gamma rays caused by the decay of the sought after particles. Apart of their intensity, what also interests them is the spatial trajectory of the high-energy rays. In order to detect the 2D-position of the gamma rays, they have invented a very clever strip array configuration. Let me explain, here’s another sketch:

Particle incidence angle detection using parallel strip configuration

A falling particle would have a higher probability of generating electron-hole pairs in the strip which is crossed by the X-ray photon, which already creates a kind of a 1-dimensional readout. To obtain the angular information, the adjacent strips could also be read-out and a particle correlation can be reconstructed. In other words, if the gamma ray happens to fall with some angle of e.g. 45 degrees, it will thus generate electron-hole pairs in two or three adjacent silicon strips. This gives us already almost 2D particle trajectory information. However, CERN engineers have decided to expand the technique even further, by adding another cross-pair of detectors underneath the upper set:

Hybrid X- and Y- direction parallel strip sensor configuration

That way not only they can extract position and angular information in the x-direction, but also the y-direction, which, by using some post-processing provides accurate particle intensities and trajectories. But how can these PN silicon strips be read out?

The simplest method in reading out thousands of strips, is the use of an integrated charge amplifier and digitization electronics per each channel. Charge sensitive amplifiers have not been very “widely” used in the past with passive pixel CMOS image sensors, and have proven to be very suitable for single detector readout. These are still used in single-line CMOS line scan sensors due to their low-noise capabilities for low detector capacitance.

Typically, operational amplifier-based integrators using an integrating capacitor in the feedback are a commonly used scheme which is sketched below:

A basic charge amplifier topology for strip sensor readout

These amplifiers have high input impedance, they integrate weak charge pulses and convert them into voltage pulses for amplification and then buffer the output for readout from the next block in the chain. Because of that operation, this type of amplifier is called a “charge amplifier”. The first stage of a charge amplifier is usually a low-noise differential pair and its open-loop gain is set sufficiently high so that its amplification is not influenced by the detector capacitance which reduces the gain in the feedback. The output stage is a low-impedance buffer so it could drive the next circuits in the chain, typically an S/H stage of an ADC.

When particle decay rays strike the silicon strips, signal charge pulses Qs are generated, with an amplitude proportional to the particle energy. Due to this charge generation, the input potential of the charge amplifier lifts up and during the same time, a potential with reverse polarity appears at the output, due to the negative feedback amplifier. However, because the amplifier’s open-loop gain is sufficiently large, its output potential works through the feedback loop so that it causes the input terminal’s potential drop to zero, after some settling time dependent on the unity-gain bandwidth of the opamp itself. As a result, the signal charge pulses Qs are integrated to the feedback capacitance Cf and the output’s voltage changes according to the integrated charge. At that moment, since the feedback resistor Rf for DC is connected in parallel to the feedback capacitor Cf, the output voltage slowly discharges with the time constant determined by τ=Cf · Rf. The output voltage of such a charge amplifier scheme is dampened by the size of the feedback capacitor Cf, thus Qs and Cf must be chosen wisely to fulfill the specifically desired dynamic range. As a result it can be observed that the noise performance and dynamic range of this readout scheme is of highest trade-off. Increasing the dynamic range, leads to a lower swing on the capacitor and hence increases noise, the reverse is also applicable.

Note that the ATLAS detector has a total of over 200 m2 (square meters!!!) of pure detector strips! With a strip size of 0.01mm by 40cm we get a pretty decent number of about 50 000 strips and readout channels respectively. With such a huge set of sensors both ATLAS and CMS rely on the statistical significance of their measurements and the weird correlation in the slight gamma peaks, might truly be caused by a completely new fundamental particle. However, the readout complexity of such an enormous set of sensors is colossal, which makes induction of errors a plausible explanation as well.

Fingers crossed that all the sensing electronics works flawlessly and that all abnormal peaks detected are due to a newly detected particle.

# Chiseling out The Chip!

This post may be a bit redundant with the info I added in the other place, but I am excited, so I felt the need to rewrite some of it here.

Le Chip! This work took a while. To celebrate, I thought it deserves a few words in the blogs. During the past year or so, I was/have-been/will-continue-to-be working on an image sensor ADC testchip. It was finally taped out yesterday! What’s left now is some additional gastronomical work on the tapeout cake and the drainage of a rusty bottle of champagne.

The chip in all its ugly majesty with all these redundant power pads and LVDS pairs.

The core of the testchip is a fast 12-bit column-parallel ramp ADC at 5u pitch, utilizing some special counting schemes to achieve the desired 1us ramp time at slow clock rates. Alongside, to be able to fully verify the pipelined CDS functionality and crosstalk, I’ve built a pixel array in line-scan configuration, some fast LVDS drivers, clock receivers, references, state machines, a few 8-bit iDACs, bond pads, ESD, and some other array-related stuff, all from scratch! The chip has a horizontal resolution of 1024 and 128 lines with RGBW color filters and microlenses.

On the top-left corner there are some experimental silicon photomultipliers and SPAD diodes. These I plan to measure for fun and I promise to post the results in any of the two blogs.

Unfortunately, this chip wouldn’t yield tons of publicaiton work, apart from the core ADC architecture and comparator. To test the ADC one needs a whole bunch of other fast readout blocks, which in the end are not something novel, but yet, one needs them and designing these takes time. Finishing up this test system was a lot of work and I realize that it might be a bit risky and ambitious to be doing this as part of a doctorate. What if it fails to work because a state machine had an inverted signal somewhere? Or the home-made ESD and pads suffer from latch-up? Or the LVDS driver CMFB is unstable and I cannot readout data out? Or there is a current spike erasing the content of the SRAM? Or, or, or ?

We university people don’t have the corporate power to tapeout metal fixes twice a month until we’re there. I probably have another two or three chip runs for my whole doctorate. It may therefore be better (and more fun) to stick with small but esoteric modules, which one can verify separately and have time to analyze in detail. But hey, I’ll quote a colleague here: “It is what it is, let’s think how we can improve things.”

Finally, I have added this little fella who I hope will be my lucky charm.

Mr Le Duck!

With his 15um of height, could he compete in the annual “smallest duck on the planet” contest? Cheers!

# Circuit diagram symbols from circuitikz

When it comes to drawing circuit diagrams for publication work (e.g. books, articles, posters) there has always been a dilemma around which drawing methodology to choose. Everyone wants to have superior quality schematic diagrams, designed in zero or negative time. The pool of drawing tools for circuit diagrams in the galaxy of internet is so huge, and yet, I have not seen any well integrated and universal tool for this simple task of drawing lines and connecting dots. As with many open-source tools, what seems to be missing is a “good integration”, this “good integration” however, appears to be a hard NP-complete problem.

With this post I am not getting any further with the solution of the problem, but I wanted to share a crude solution for creating tikz-like quality circuit diagrams, without having to spend days in tikz coding like a monkey to create a simple RC schematic. If you are not familiar with tikz and the circuitikz package, click on the links to read more.

Going straight to the point – here is a pdf file containing a “database card” of all available till this date circuitikz symbols. Of course, you can find the symbols in the package documentation, however, these are spread among the 60 page manual which is rather difficult for indexing and import in Inkscape.

Now when I have a compressed document with all symbols, I can easily import the ones I need in Inkscape and continue drawing the usual way. Here is the tikz input file used for generation.

And in case you need a high resolution raster version of the database you can find one below.

circuitikz v.0.3 database card

# Applied chaos theory

Today I am having fun with a very nerdy circuit – Chua’s circuit. An electronic circuit that exhibits chaotic behaviour. I had a hard time getting this circuit to oscillate, but finally, after some prayers, throwing beans and doing black magic here it is:

Chua’s circuit

Heheh, looks terrible, but works. Here are some cool pictures of the Lorenz attractor. I was not able to spread the two twirls further, as my LC tank (in fact gyrator-capacitor tank) would stop oscillating.

Lorenz attractor curves tiral 1

Lorenz attractor curves tiral 2

Lorenz attractor curves tiral 3

Lorenz attractor curves tiral 4

And in case you also want to see how it sounds like and what my setup was here’s a short video clip:

# How long are your wires?

Lately I have been busy working on my analog to digital converters, I have gotten up to the phase of laying out the transistors and interconnect. A question struck me – how long are my wires? I mean, the total sum of lengths of all my wires? Usually the average bus length does not exceed a few hundred micrometers before the signals are being re-buffered, but we have hundreds, if not thousands of them sometimes. To illustrate what I mean, let’s have a sneak on my chip’s interconnect:

Here are a few of the metal layers shown separately. Sorry, can’t afford to show you the rest of the system and more than the metal layers as it’s still a secret, shhh… : )

A close view of vertical interconnect

Vertical interconnect

Horizontal interconnect

A close view

Horizontal interconnect two

Considering the fact that some SoCs can have up to 16 metal layers, we can continue our list forever. Notice the ruler showing the scale of the first figure, the unit is in micrometers. I was wondering what is the best way to calculate all sums, however Domenico Pacifici has done this analysis in his PhD thesis before me and I dare to reprint one of his figures.

Total interconnect length in km/cm2 vs year of process development

Wowsh, I had guesses that it may be in the order of hundreds of meters, but 10km? Also notice the log scale, nicely matching with Moore’s law. Remember also that in 2008 the cutting-edge process nodes were at about 90 to 65nm. Some large SoCs may reach areas of about 5 $cm^{2}$, this means that the computer chips we have in an average town contain enough wire to probably reach the Moon? Impressive! Now keep calm and continue pushing polygons!

# Gambling with electronics… literally

Finally… I am done with my exams and there is time for some fun.

No, I didn’t spend a fortune in a casino. But I wanted to try some of the “games” that could be assembled with my Conrad kit which includes a breadboard and some basic elements. The binary die caught my eye (woah, a rhyme!) Most tabletop games require a die or two. It’s usually a plain old six-sided guy, although if you’ve played Dungeons & Dragons, you know there are some bizarre looking cousins of this die. The most famous being the d20, or a regular icosahedron if you prefer the geometric term. So there I was, dreaming of how spectacular it would be if I appeared at our next D&D session with a light show on a breadboard which is actually a 20-sided die.

However, I had to make the boring 6-sided one first. The idea is to use 3 LEDs of different colour, assigning the numbers 1, 2 and 4 to each colour. Then, while a button is pushed, the LEDs will change their condition quickly and make it impossible to recognise any number. After the button is released, the LEDs remain in a stable condition and the rolled number can be read. It is the sum of the LEDs that remain lit.

The circuit used, with NAND gate, binary counter, resistors, capacitor and the three LEDs

In theory this is great. The cycle for switching through the conditions is achieved with the NAND-gate. The resistor R1 and the capacitor C1 determine the cycle speed. The cycle is only applied to the binary counter (IC2) when the button is pushed. If the button is not pushed, the cycle input (CPU) is connected to ground across the pull-down resistor R2. So far so good… here’s the messy part:

From the Conrad manual:

The inputs D0 to D3 specify that the counter is to start at 1. For this, only the input D0 (pin 15) is connected to high. The inputs D1 to D3 are connected to ground (low level). The counter reading is always reset to 1 when the pin PL (11) is pulled to low level. This should be done after the number 6, since the number 7 is not permitted. Resetting to 1 takes place with the number 7; then all outputs (Q0 to Q3) have a high level. The three NAND-gates are switched to result in a NAND gate with three inputs. For three high levels at the inputs, a low level results at the output of IC1D (pin 11). The low level thus resets the counter reading to 1. Resetting is so fast that the counter reading 7 (all at high level) is not visible.

Alright, so I hooked up everything, I checked the circuit and here’s what happened:

The circuit, ready to rock

Pressing the button and…

Red and only red. Checked everything again – no change. Is red my lucky number, or I just messed up big time? Then I noticed the button was pretty wobbly, it actually jumped away from the board when I tried to push it harder and let it go. So… My plan for troubleshooting is: set it up without a button (I’ll use wires instead); check for other errors; check for errors in the circuit itself and find alternative ways for building dice.

This post and project is indeed a failure… For now. Hopefully, with some holidays coming, I’ll have the time for a follow-up and a fix. Meanwhile, if anyone who stumbles upon this has something to say, please do. Surely tabletop games will be perfectly fine without my clumsy circuit dice, but I still wanna do this. Maybe other gambling tools in the future too. The ways of achieving randomness via electronics fascinate me!

# An analog designer’s most favorite circuit

It was about time that I start writing about circuits. I chose this one as it is the very first OTA circuit I used in practice and it is by far one’s choice consideration number one when it comes to designing an ordinary general purpose operational amplifier. It’s like the E=MC2 in physics! The architecture is so simple, yet provides an easy to design differential to single-ended conversion circuit with an increased slew rate capability.

Let’s hop-over to the beautiful architecture and derive its main parameter – the DC gain or Ao.

A current mirror OTA

However first, let’s try to identify the main sub-blocks of this circuit (divide and conquer). Transistors M1, M2 together with M3 and M4 form a simple differential amplifier, M0 acts as a current source and provides the main bias for the whole amplifier. Moving forward we can identify three current mirrors, these are M4 w/ M6, M3 w/ M5 and M7 w/ M8.

For a symmetrical design we normally want to keep the ratios (B) between M3 w/ M5 and M4 w/ M6 equal. The third current mirror formed by M7 w/ M8 would normally get a ratio of 1 if B is the same for M5 and M6, it is beneficial to set K = 1 and boost B to save some layout area. Let’s start upside down and show that the slew-rate would be simply determined by I0 and the factor B. In other words:

$SR = \frac{(I_{0}/2)B}{C_{L}}$

Good. Moving over to the DC gain, one can follow a few approaches:

1) Draw an ESSM, apply Kirchoff’s current laws and solve the corresponding system of linear equations (I’ll leave this to the academics as this is the official method and can be found in every analog design book)

2) Instead, follow your engineering intuition and find an approximate DC gain expression, which is obvious, why bother solving systems of equations, save those for difficult times.

We can assume that we have no channel length modulation effects i.e. $\lambda = 0$ or the transistor’s transconductance $g_{m}$ is much larger than the output conductance $g_{ds}$. Now the beauty, let’s split the circuit into a few primitives, think single stage amplifiers e.g. a common-source:

A common source amplifier

We know that Ao is to a first order approximation $-g_{m}R_{L}$. This is not the case for sub-micron processes, but still gives us a good enough approximation. We can also identify the other blocks – the current mirrors.

Current mirror M4 w/ M6

Current mirrors M3 w/ M5 and M7 w/ M8

These are just copying currents and effectively provide us with a ratio-amount of gain. After the current is copied, it is pushed/terminated into the output node, i.e. imagine what the “termination resistors” should be at the output node, remember the CS amp stage? The same applies for the other two mirrors (note how M7 w/ M8 form an elegant differential to single-ended conversion). So, by just bypassing the copied currents we can again remember the CS amplifier and its output load. So, intuitively the output impedance of our amplifier would be equal to $R_{outPFET}||R_{outNFET}$. We can once again go back to our CS amplifier thinking and substitute the symbols in the “engineering” way so we get:

$A_{0} = g_{m1}.B.R_{outPFET}||B.K.R_{outNFET}$

Which if we think of conductance would simply be:

$A_{0} = g_{m1}.B.\frac{1}{g_{dsPFET}}||B.K.\frac{1}{g_{dsNFET}}$

Thinking of output conductance however we can note that while changing the factor B, we increase the output current, which in another respect decreases the output impedance of our amplifier with the same magnitude, thus reducing the gain or leaving out the mirroring factor B out of the game. So, we can conclude that in general the DC gain is:

$A_{0} = g_{m1}.R_{outPFET}||R_{outNFET}$

Which is why the DC gain of this OTA architecture is relatively low and limited to what can be squeezed out of the differential pair. One common trick for increasing the DC gain at the cost of decreasing the 3dB cutoff freuqncy is by adding output cascodes:

Adding a pair of cascodes at the output stage

As shown on the picture, one can imagine those as effectively adding two more resistors in series at the output stage, well, to a primitive first order approximation. Alternatively, following your intuition, here is why adding resistors change the amplifier’s 3dB cutoff frequency and not the unity-gain frequency. Think RC low-pass filtering this time, by increasing R we increase the time constant $\tau$ thus the 3dB cutoff drops down.

Another way of “imagining” what the output cascodes does to our OTA transfer function

About the stability in feedback loops of this current mirror OTA we can in general hint that it may be a good idea to keep this amplifier dominant output load compensated and have in mind that the current mirrors M4 w/ M6 and M3 w/ M5 are contributing with a non-diminant pole (due to their gate-source and diffusion capacitances) and in cases of increased mirroring factor B lead to a significant reduction in the phase margin of the loop. A zero is also introduced at M7 w/ M8 mirroring, but in general should not be of concern due to the usually small mirroring ratio in the third mirror.

With this my simple introduction leads to an end. To be continued with “An analog designer’s second most favorite circuit” 🙂