# Gambling with electronics… literally

Finally… I am done with my exams and there is time for some fun.

No, I didn’t spend a fortune in a casino. But I wanted to try some of the “games” that could be assembled with my Conrad kit which includes a breadboard and some basic elements. The binary die caught my eye (woah, a rhyme!) Most tabletop games require a die or two. It’s usually a plain old six-sided guy, although if you’ve played Dungeons & Dragons, you know there are some bizarre looking cousins of this die. The most famous being the d20, or a regular icosahedron if you prefer the geometric term. So there I was, dreaming of how spectacular it would be if I appeared at our next D&D session with a light show on a breadboard which is actually a 20-sided die.

However, I had to make the boring 6-sided one first. The idea is to use 3 LEDs of different colour, assigning the numbers 1, 2 and 4 to each colour. Then, while a button is pushed, the LEDs will change their condition quickly and make it impossible to recognise any number. After the button is released, the LEDs remain in a stable condition and the rolled number can be read. It is the sum of the LEDs that remain lit.

The circuit used, with NAND gate, binary counter, resistors, capacitor and the three LEDs

In theory this is great. The cycle for switching through the conditions is achieved with the NAND-gate. The resistor R1 and the capacitor C1 determine the cycle speed. The cycle is only applied to the binary counter (IC2) when the button is pushed. If the button is not pushed, the cycle input (CPU) is connected to ground across the pull-down resistor R2. So far so good… here’s the messy part:

The inputs D0 to D3 specify that the counter is to start at 1. For this, only the input D0 (pin 15) is connected to high. The inputs D1 to D3 are connected to ground (low level). The counter reading is always reset to 1 when the pin PL (11) is pulled to low level. This should be done after the number 6, since the number 7 is not permitted. Resetting to 1 takes place with the number 7; then all outputs (Q0 to Q3) have a high level. The three NAND-gates are switched to result in a NAND gate with three inputs. For three high levels at the inputs, a low level results at the output of IC1D (pin 11). The low level thus resets the counter reading to 1. Resetting is so fast that the counter reading 7 (all at high level) is not visible.

Alright, so I hooked up everything, I checked the circuit and here’s what happened:

Pressing the button and…

Red and only red. Checked everything again – no change. Is red my lucky number, or I just messed up big time? Then I noticed the button was pretty wobbly, it actually jumped away from the board when I tried to push it harder and let it go. So… My plan for troubleshooting is: set it up without a button (I’ll use wires instead); check for other errors; check for errors in the circuit itself and find alternative ways for building dice.

This post and project is indeed a failure… For now. Hopefully, with some holidays coming, I’ll have the time for a follow-up and a fix. Meanwhile, if anyone who stumbles upon this has something to say, please do. Surely tabletop games will be perfectly fine without my clumsy circuit dice, but I still wanna do this. Maybe other gambling tools in the future too. The ways of achieving randomness via electronics fascinate me!

# An analog designer’s most favorite circuit

It was about time that I start writing about circuits. I chose this one as it is the very first OTA circuit I used in practice and it is by far one’s choice consideration number one when it comes to designing an ordinary general purpose operational amplifier. It’s like the E=MC2 in physics! The architecture is so simple, yet provides an easy to design differential to single-ended conversion circuit with an increased slew rate capability.

Let’s hop-over to the beautiful architecture and derive its main parameter – the DC gain or Ao.

A current mirror OTA

However first, let’s try to identify the main sub-blocks of this circuit (divide and conquer). Transistors M1, M2 together with M3 and M4 form a simple differential amplifier, M0 acts as a current source and provides the main bias for the whole amplifier. Moving forward we can identify three current mirrors, these are M4 w/ M6, M3 w/ M5 and M7 w/ M8.

For a symmetrical design we normally want to keep the ratios (B) between M3 w/ M5 and M4 w/ M6 equal. The third current mirror formed by M7 w/ M8 would normally get a ratio of 1 if B is the same for M5 and M6, it is beneficial to set K = 1 and boost B to save some layout area. Let’s start upside down and show that the slew-rate would be simply determined by I0 and the factor B. In other words:

$SR = \frac{(I_{0}/2)B}{C_{L}}$

Good. Moving over to the DC gain, one can follow a few approaches:

1) Draw an ESSM, apply Kirchoff’s current laws and solve the corresponding system of linear equations (I’ll leave this to the academics as this is the official method and can be found in every analog design book)

2) Instead, follow your engineering intuition and find an approximate DC gain expression, which is obvious, why bother solving systems of equations, save those for difficult times.

We can assume that we have no channel length modulation effects i.e. $\lambda = 0$ or the transistor’s transconductance $g_{m}$ is much larger than the output conductance $g_{ds}$. Now the beauty, let’s split the circuit into a few primitives, think single stage amplifiers e.g. a common-source:

A common source amplifier

We know that Ao is to a first order approximation $-g_{m}R_{L}$. This is not the case for sub-micron processes, but still gives us a good enough approximation. We can also identify the other blocks – the current mirrors.

Current mirror M4 w/ M6

Current mirrors M3 w/ M5 and M7 w/ M8

These are just copying currents and effectively provide us with a ratio-amount of gain. After the current is copied, it is pushed/terminated into the output node, i.e. imagine what the “termination resistors” should be at the output node, remember the CS amp stage? The same applies for the other two mirrors (note how M7 w/ M8 form an elegant differential to single-ended conversion). So, by just bypassing the copied currents we can again remember the CS amplifier and its output load. So, intuitively the output impedance of our amplifier would be equal to $R_{outPFET}||R_{outNFET}$. We can once again go back to our CS amplifier thinking and substitute the symbols in the “engineering” way so we get:

$A_{0} = g_{m1}.B.R_{outPFET}||B.K.R_{outNFET}$

Which if we think of conductance would simply be:

$A_{0} = g_{m1}.B.\frac{1}{g_{dsPFET}}||B.K.\frac{1}{g_{dsNFET}}$

Thinking of output conductance however we can note that while changing the factor B, we increase the output current, which in another respect decreases the output impedance of our amplifier with the same magnitude, thus reducing the gain or leaving out the mirroring factor B out of the game. So, we can conclude that in general the DC gain is:

$A_{0} = g_{m1}.R_{outPFET}||R_{outNFET}$

Which is why the DC gain of this OTA architecture is relatively low and limited to what can be squeezed out of the differential pair. One common trick for increasing the DC gain at the cost of decreasing the 3dB cutoff freuqncy is by adding output cascodes:

Adding a pair of cascodes at the output stage

As shown on the picture, one can imagine those as effectively adding two more resistors in series at the output stage, well, to a primitive first order approximation. Alternatively, following your intuition, here is why adding resistors change the amplifier’s 3dB cutoff frequency and not the unity-gain frequency. Think RC low-pass filtering this time, by increasing R we increase the time constant $\tau$ thus the 3dB cutoff drops down.

Another way of “imagining” what the output cascodes does to our OTA transfer function

About the stability in feedback loops of this current mirror OTA we can in general hint that it may be a good idea to keep this amplifier dominant output load compensated and have in mind that the current mirrors M4 w/ M6 and M3 w/ M5 are contributing with a non-diminant pole (due to their gate-source and diffusion capacitances) and in cases of increased mirroring factor B lead to a significant reduction in the phase margin of the loop. A zero is also introduced at M7 w/ M8 mirroring, but in general should not be of concern due to the usually small mirroring ratio in the third mirror.

With this my simple introduction leads to an end. To be continued with “An analog designer’s second most favorite circuit” 🙂

# The terahertz band

Today, while listening to a talk about protein vibrations and terahertz imaging I was quite surprised to see a diagram of the electromagnetic wave spectrum with a little twist which I thought might be fun to share here. So, here it is:

The THz gap!

Practically nothing new, apart from the emphasis on the Terahertz gap which even with today’s technological advancements still exists. It appears that many proteins and organic compounds have a resonant frequency in the THz range and it may be quite beneficial to be able to receive and transmit electromagnetic waves in this range so as to perform diagnosis or potential treatment. Just as a side note and comparison, hemoglobin appears to resonate at 0.5-0.6 THz, hmm… it seems like our bodies are very good transmitters in the THz band.

What do you think will be the name of this new science which would hopefully, one day, conquer that gap? Terahertzonics, ElectroPhotonics, RadioPhotonics? Maybe there is a name for it already?

# Visible light communications

Not long ago I listened to a talk led by Dr Sujan Rajbhandari giving a brief overview of visible light communications and some in-depth details about one of the latest projects happening at the optical wireless communications group here.

Let me give you a brief outline of their system and some of the main challenges in visible light communication (from now on abbreviated as VLC). Let’s start by stating some of the challenges:

1. VLC can not be established through solid medium i.e. visible light is blocked by walls, obstacles etc…

2. P.1 may be considered as something positive as it allows us to implement a very secure communication link; light does not escape the room as opposed to an RF Wi-Fi signal for example. On the other hand, the former obstructs us from achieving high coverage too.

3. Visible light sources (bar some lasers) have a quite low bandwidth as compared to what is possible to achieve with an RF modulator. I.e. Dr. Rajbhandari noted that the highest bandwidth LED they used, which was by the way custom made, had a BW of ~50MHz (on top of my head, may be more?). 50MHz gives us a maximum theoretical link BW of 25MSPS at one pulse-amplitude level (on-off keying). Adding-up the receiver (photodiode) bandwidth limitations, communication medium, noise, etc… drops down the link bandwidth dramatically.

4. External light happens to be a severe noise contributor to the link. I.e. we want to be in a bright lit room and still use a VLC link, however the white? daylight shines the receiver (photodiode) too, we are thus getting a huge interference and practically a failure to establish a link

5. What if my lamp (transmitter) does not shine my receiver directly, but via a reflection? More SNR losses and an increase of the bit error rate (BER).

From the few points above it becomes obvious that inventing a good VLC system is not an easy task. Even so, the group here reported connection speeds of 3Mbps at a distance of one meter, which currently appears to be a world speed record in VLC systems.

I would like to share some pictures of their excellent work (huge thanks to the group for letting me have a look at their device and for organizing the interesting weekly seminars in optical communications).

The visible light communication link setup.

VLC Transmitter – Left; VLC Receiver – right; link distance – 1m

A close view of the transmitter and its colimating lens

TX driver with pulse-amplifde modulation controller

The RX side, lens and active photodiode sensor RX matrix.